Simulink Models from Algorithms to Silicon

The algorithm development cycle can eat into the timelines of reference model development and fixed point conversion. This can further push out the hardware development cycle (RTL). Altera Corporation has developed a methodology that can leapfrog incorporating the algorithm changes all the way to RTL. This methodology demonstrates the versatility of using a single Simulink^® model to incorporate and validate algorithmic changes (block/system performance), fixed-point conversion effects, and finally generate synthesizable RTL (leveraging HDL Coder™) from the same model. In addition, the fixed-point Simulink model can be further extended to generate a bit-accurate DPIC model for RTL verification.

In this session, see a demonstration of a real-life wireless receiver algorithm (part of an entire wireless modem being developed) that will: -    Run the Simulink reference model in floating point mode and compare against a MATLAB ^® algorithm reference.-    Show seamless switching to use the same Simulink reference model in fixed point mode, with fixed point effects.

You will learn a design methodology to use a single Simulink reference model for performance evaluation of algorithms, evaluate the model's fixed-point performance, and finally generate synthesizable RTL.