NEXYS4-DDR FPGA Card in Matlab-Simulink FPGA in the Loop (FIL) connection

Matlab Simulink supports Digilent Nexys4 Artix 7 board for FIL Simulation (FPGA-in-the-loop). I'm using the Nexys4 DDR Artix 7 board for FIL Simulation. But I always get the following error.

    source_vivado_program.cmd
    # set chain_position 0
    # connect_hw_server -host localhost -port 60001
    ERROR: [Common 17-170] Unknown option '-host', please type
    'connect_hw_server -help' for usage info.
    INFO: [Common 17-206] Exiting Vivado at Fri Apr 08 21:59
    2016...
I set myself the board information for Nexys4-DDR in Matlab-Simulink FPGA in the Loop (FIL) connection for Hardware and Simulink communication that I chose "Create custom board" section. I entered all the desired settings. But, again, it gave following the same error. I use Xilinx Vivado 2015.4 and Matlab R2015a programs and I'm using the JTAG connection. Could anyone help about this situation?