Why is the Equivalent Number of Bits (ENOB) in my SAR ADC model and testbench greater than the actual number of bits?

In the Mixed-Signal Blockset example of a 'SAR ADC' and 'ADC Testbench' found by referring to the link below:

https://www.mathworks.com/help/msblks/gs/DesignAndEvaluateSARADC.html

the number of bits in the ADC is 10 and the Equivalent Number of Bits (ENOB) is 10.15. How is it possible that the ENOB is greater than the number of bits?

Answer 1

[MathWorks Support Team]

The ENOB calculation is based on SINAD. As a result of using SINAD to calculate the ENOB, if the noise floor is very low the ENOB can exceed the actual number of bits. This is the case in this simulation. Making the converter less ideal should decrease this to reasonable levels. Possible methods of introducing noise include increasing Aperture Jitter or adding noise to the analog input signal.

In this case, the 'RMS Aperture Jitter' in the 'ADC Testbench' block can be increased to lower the ENOB to more realistic, reasonable levels. More information about the 'RMS Aperture Jitter' parameter in the 'ADC Testbench' block can be found by referring to the link below:

https://www.mathworks.com/help/msblks/ref/adctestbench.html#mw_6093a1ae-4af7-4a05-902b-7e2d806cee6d