How do you generate HDL code for the Artix-7 family of boards? What is the recommended workflow for this?

I am trying to generate VHDL code for a standalone application on an Artix-7 (35t) board. What is the recommended workflow for doing this?

The requirements are: 

- it should work as a stand-alone board 

- the generated code should include I/O port definitions and clock specifications 

Does HDL coder provide support for this through the "FPGA Turnkey" workflow?

Answer 1

[MathWorks Support Team]

HDL Coder supports Vivado-based Xilinx FPGA prototyping using the "IP Core Generation" workflow, instead of the "FPGA Turnkey" workflow. The following links provide some useful starting points for this workflow:

1. Getting started with Xilinx Zynq Platform: https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-xilinx-zynq-platform.html

A similar workflow can be used to generate HDL code for custom target platforms. A complete list of supported third party tools and hardware for HDL code generation can be found here: https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-support.html. This includes boards from the Xilinx Art-7 family such as the Artix-7 35T Arty FPGA.

However before you can use this workflow, you will need to create a custom "Reference Design" for the Artix-7 FPGA board, including the I/O port definitions and clock specifications. HDL Coder introduced the concept of "Reference Design" so that you define the FPGA platform around the generated HDL algorithm IP.

The following shipping examples explain how you can go about building a reference design:

1. Digilent® Zybo board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html
2. Digilent® Zybo board: https://www.mathworks.com/help/hdlcoder/ug/authoring-a-reference-design-for-audio-system-on-a-zybo-board.html 
3. Zedboard: https://www.mathworks.com/help/hdlcoder/ug/authoring-a-reference-design-for-audio-system-on-a-zynq-board.html

Support packages are available on File Exchange to support users with IP core generation for custom FPGA platforms with Xilinx® Vivado® IP Integrator:

1. HDL Coder Support Package for Xilinx Zynq Platform: https://www.mathworks.com/matlabcentral/fileexchange/40447-hdl-coder-support-package-for-xilinx-zynq-platform
2. Embedded Coder Support Package for Xilinx Zynq Platform: https://www.mathworks.com/help/ecoder/xilinxzynq7000ec-support-pkg.html
3. Avent offers Simulink support package for easier HDL Code generation: https://www.mathworks.com/matlabcentral/fileexchange/66004-avnet-minized-support-package-for-simulink.

For a complete confirmation of board compatibility, consider various other toolboxes, functions and blocks used in your design and verify they are supported for HDL code generation.