Hardware and Software Requirements

To run this example, you must have the following software and hardware installed and set up:

Setup

Step 1: Set up the FPGA board. Verify that the Xilinx Zynq-7000 ZC706 board is connected to the host computer through an Ethernet cable. The Ethernet cable is used to program and communicate with the board.

Step 2: Set up the SD card. For details, see steps 1 through 4 in Ethernet MATLAB as AXI Master for Zynq SoC Devices.

Step 3: Set up the Xilinx Vivado® tool path. Use your Xilinx Vivado installation path when executing the command in MATLAB. For example, enter this command at the MATLAB command prompt.

>> hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2019.2-mw-0\Win\Vivado\2019.2\bin');

Create a folder outside of the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.

Set the current directory in MATLAB to the folder that you created. For example enter this command at the MATLAB command prompt.

>> cd C:\MyTests

Copy the example files into the current directory by executing this command at the MATLAB command prompt.

>> copyXilinxFPGAExampleFiles('ethernetaximasterzynq');

Unzip the imagerotation_ip.zip file to add the image rotation IP to the User Repository in your Vivado project.

>> unzip(fullfile('ipcore','imagerotation_ip_v1_0.zip'),fullfile('ipcore','imagerotation_ip_v1_0'));

Create a Vivado project using this command. This project contains an IP Integrator block diagram and a constraint file.

>> system('vivado -mode batch -source createproject.tcl')

This process completes in about a minute. A Vivado project named "ethernetaximasterzynq.xpr" is created in your current directory.

Open the generated Vivado project in GUI mode by double-clicking the project in a file browser or by executing this command at the MATLAB command prompt.

>> system('vivado ethernetaximasterzynq.xpr &')

Step 4: In the Vivado GUI, open the block diagram design file design_1.bd. You can find this file in the source file subwindow.

Open the Address Editor window to view the address mapping of mig_7series_0 (memory controller) and imagerotation_ip.

These are the imagerotation_ip registers and their corresponding physical locations.

Note: Skip step 5 and 6 to use the pregenerated bitstream and the DTB file copied to the current working directory.

Step 5: Generate the FPGA programming file.

Click Generate Bitstream on the left of the Vivado window to generate the FPGA programming file. Vivado might prompt you to save the project before moving forward. Vivado generates bitstream file in 5 to 10 minutes.

Step 6: Generate the device tree blob (DTB) file.

To compile a DTB file, you need a device tree compiler (DTC) on a Linux machine. If a DTC is not installed, execute these commands in Linux console window.

% sudo apt-get update -y

% sudo apt-get install -y device-tree-compiler

After successful installation of DTC, to generate a DTB file, open the board-specific DTS file to provide the FPGA memory information as shown below.

Alternatively, you can use the DTS file provided for this example: C:\MyTests\devicetree_zc706_image_rotation.dts.

Generate a DTB file from the DTS file by executing this command.

% dtc -I dts -O dtb devicetree_zc706_image_rotation.dts -o devicetree_zc706_image_rotation.dtb

Step 7: Program the FPGA in MATLAB by entering this command at MATLAB command prommpt.

>> loadBitstream('ZC706','ethernetaximaster_zynq_zc706.bit','devicetree_zc706_image_rotation.dtb');

Run the Design

To run the design, run the ethernetaximasterzynq_tb.m file at MATLAB command prommpt from the current working folder.

>> ethernetaximasterzynq_tb

The script runs the design from MATLAB by creating an AXI-Master object and plots the input and output images as shown.