IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

This example uses:

This example uses Ethernet based MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated registers. MATLAB as AXI Master provides access to FPGA registers from MATLAB directly. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

Requirements

Intel Quartus Prime, with supported version listed in the HDL Coder documentation
Arrow DECA MAX 10 FPGA evaluation kit
HDL Coder™ Support Package for Intel FPGA Boards
HDL Verifier™ Support Package for Intel FPGA Boards
USB-JTAG Cable
Cross-over Ethernet Cable

Arrow DECA MAX 10 FPGA evaluation kit

Example Reference Design

The reference design, "MATLAB as AXI Master - Ethernet", uses MathWorks IP and a MATLAB command line interface for issuing reads and writes. Note that this design requires an HDL Verifier license to use. The plugin_rd.m for this reference design is shown below:

function hRD = plugin_rd()
% Reference design definition

%   Copyright 2016-2018 The MathWorks, Inc.

% Construct reference design object
hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Altera QUARTUS II');

hRD.ReferenceDesignName = 'MATLAB as AXI Master - Ethernet (requires HDL Verifier)';
hRD.BoardName = 'Arrow DECA MAX 10 FPGA evaluation kit';

% Tool information
hRD.SupportedToolVersion = {'17.1'};

%% Add custom design files
% add custom Qsys design
hRD.addCustomQsysDesign('CustomQsysPrjFile', 'system_soc.qsys');
hRD.CustomConstraints = {'system_soc.sdc','create_project_eth_deca.tcl'};
hRD.CustomFiles = {'phy_to_gmii'}; % Adding other files for custom IP core

% Add ip from support package
msg = message('hdlcommon:plugin:IPRepositoryHDLVerifierAlteraNotFound',...
 '<a href="matlab:matlab.addons.supportpackage.internal.explorer.showSupportPackages({''HDLVALTERA''}, {''tripwire''});">download</a>').getString;
hRD.addIPRepository('IPListFunction','hdlverifier.fpga.quartus.iplist', 'NotExistMessage', msg);

%% Add interfaces
% add clock interface
hRD.addClockInterface( ...
    'ClockConnection',     'altpll_0.c0', ...
    'ResetConnection',     'clk_0.clk_reset',...
    'DefaultFrequencyMHz', 50);

% add AXI4 slave interfaces
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'udp_matlab_axi_master_0.axi4_udp', ...
    'BaseAddress',         '0x0000_0000',...
    'InterfaceType',       'AXI4');                                          % [ 'AXI4-Lite'| 'AXI4' ]

% Specify Embedded Coder Support Package to use for Software Interface
hRD.EmbeddedCoderSupportPackage = hdlcoder.EmbeddedCoderSupportPackage.None;  % [ None | Zynq | AlteraSoC ]

The corresponding plugin_rd.m file for the MATLAB as AXI master reference design is located at: plugin_rd.m.

Execute the IP Core Workflow

The reference design will generate an HDL IP Core that blinks LEDs on the DECA board. The files used in the following demonstration are located at:

matlab/toolbox/hdlcoder/supportpackages/altera/+hdlipcore/+board/ArrowDECA

1. Set up the Intel Quartus™ tool path. Replace the Quartus™ installation path with your local installation

>> hdlsetuptoolpath('ToolName', 'Altera QUARTUS II', 'ToolPath', 'C:\intelFPGA\17.1\quartus\bin64\quartus.exe');

2. Open the Simulink model that implements LED blinking:

3. Launch HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.

4. Select a reference design from the drop down in step 1.2

5. Assign register ports to the "AXI4" interface. The table displays the hex offset you can use to access the register.

6. Run the remaining steps in the workflow to generate a bitstream and program the target device.

The Ethernet based MATLAB as AXI Master IP in this design has a default target IP Address of 192.168.1.2 and default UDP Prot value of 50101. Please ensure the host machine's Network Interface Card is configured accordingly.

Determining Addresses from the IP Core Report

The Base Address for an HDL Coder™ IP Core is defined in the reference design plugin_rd.m For this design, the base address is 0x0000_0000. The offsets can be found in the IP Core Report Register Address Mapping table:

HDL Verifier MATLAB as AXI Master - Ethernet Command Line Interface

If HDL Verifier support package for Intel FPGA boards is installed and the reference design "MATLAB as AXI Master - Ethernet" is selected, a simple MATLAB command line interface can be use to access the IP core generated by HDL Coder.

First, create the AXI master object:

  >> h = aximaster('Intel', 'interface', 'UDP', 'DeviceAddress', '192.168.1.2')

Then you can issue simple read and write commands. For example, to disable the DUT:

  >> h.writememory('4', 0)

To re-enable the DUT, use the following write command:

  >> h.writememory('4', 1)

To read the current counter value:

  >> h.readmemory('108', 1)

Documentation