N-bit DAC based on R-2R weighted resistor architecture
Mixed-Signal Blockset / DAC / Architectures

The R-2R DAC is one of the most common types of Binary-Weighted DACs. It consists of a parallel binary-weighted resistor bank. Each digital level is converted to an equivalent analog signal by the resistor bank.
The input/output transfer curve of the binary weighted DAC can be nonmonotonic, which means that the transfer curve can reverse its direction.

The R-2R DAC architecture is low resolution and consumes more power due to the large number of resistors required to implement the architecture.
digital — Digital input signal to DACDigital input signal to DAC, specified as a scalar.
Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | fixed point
start — External clock to start conversionExternal clock to start conversion, specified as a scalar. This port determines when digital-to-analog conversion process starts.
To enable this port, select Use external start clock in the General tab.
Data Types: double
analog — Converted analog output signalConverted analog output signal, returned as a scalar.
Data Types: double
ready — Determines whether digital-to-analog conversion is completeDetermines whether the digital-to-analog conversion is complete, returned as a scalar.
To enable this port, select Show ready port in the General tab.
Data Types: double
Number of bits — Number of bits in input word5 (default) | positive real integerNumber of bits in the input word, specified as a unitless positive real integer. Number of bits determines the resolution of the DAC.
Block parameter:
NBits |
| Type: character vector |
| Values: positive real integer |
Default:
5 |
Data Types: double
Input polarity — Polarity of input signal to DACBipolar (default) | UnipolarPolarity of the input signal to the DAC.
Block parameter:
Polarity |
| Type: character vector |
Values:
Bipolar|Unipolar |
Default:
Bipolar |
Use external start clock — Connect to external start conversion clockSelect to connect to an external start conversion clock. By default, this option is selected. If you deselect this option, a Sampling Clock Source block inside the Segmented DAC is used to generate the start conversion clock
Conversion start frequency (Hz) — Frequency of internal start conversion clock1e6 (default) | positive real scalarFrequency of the internal start conversion clock, specified as a real scalar in Hz. The Conversion start frequency parameter determines the conversion rate at the start of conversion.
To enable this parameter, deselect Use external start clock.
Block parameter:
StartFreq |
| Type: character vector |
| Values: positive real scalar |
Default:
1e6 |
Data Types: double
Reference (V) — Reference voltage2 (default) | real scalarReference voltage of the DAC, specified as a real scalar in volts. Reference (V) helps determine the output from the input digital code, Number of bits, and Bias (V) using the equation:
.
Block parameter:
Ref |
| Type: character vector |
| Values: real scalar |
Default:
2 |
Data Types: double
Bias (V) — Bias voltage added to output0 (default) | real scalarBias voltage added to the output of the DAC, specified as a real scalar in volts. Bias (V) helps determine the output from the input digital code, Number of bits, and Reference (V) using the equation:
.
Block parameter:
Bias |
| Type: character vector |
| Values: real scalar |
Default:
0 |
Data Types: double
Show ready port — Enable ready port on blockSelect to enable the ready port on the block. This option is deselected by default.
Enable impairments — Enable impairments in DAC simulationSelect to enable impairments such as offset error and gain error in DAC simulation. This parameter is selected. by default.
Offset error — Shifts quantization steps by specific value0 LSB (default) | real scalarShifts quantization steps by a specific value, specified as a scalar in %FS (percentage full scale), FS (full scale), or LSB (least significant bit).
Offset error is applied before Reference (V) and Bias (V).
To enable this parameter, select Enable impairments in the Impairments tab.
Block parameter:
OffsetError |
| Type: character vector |
| Values: real scalar |
Default:
0 LSB |
Data Types: double
Gain error — Error in slope of DAC transfer curve0 LSB (default) | real scalarError in the slope of the straight line interpolating the DAC transfer curve, specified as a real scalar in %FS (percentage full scale), FS (full scale), or LSB (least significant bit).
Gain error is applied before Reference (V) and Bias (V).
To enable this parameter, select Enable impairments in the Impairments tab.
Block parameter:
GainError |
| Type: character vector |
| Values: real scalar |
Default:
0 LSB |
Data Types: double
Settling time (s) — Time required for output to settle2e-7 (default) | nonnegative real scalarThe time required for the output of the DAC to settle to within some fraction of its final value, specified as a nonnegative real scalar in seconds.
Block parameter:
SettlingTime |
| Type: character vector |
| Values: real scalar |
Default:
2e-7 |
Data Types: double
Settling time tolerance (LSB) — Tolerance for calculating settling time0.5 (default) | positive real scalarThe tolerance allowed for calculating settling time, specified as a positive real scalar in LSB. The output of the DAC must settle within the Settling time tolerance (LSB) by Settling time (s).
Block parameter:
SettlingTimeTolerance |
| Type: character vector |
| Values: positive real scalar |
Default:
0.5 |
Data Types: double
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