Thread Subject:

Problem with Modelsim 6.5 and Matlab/Simulink 2012a version

Sir,
I'm using Matlab 2012a (32 bit) in my Windows 7 (64 bit) os and Altera web edition 9.1 (32bit)and Modelsim 6.5b (bit).

When I tried to RUN MATLAB EXAMPLE: Verifying Viterbi Decoder Using ModelSim
or
Creating an FPGA Domain Model (dxpcSGIO301servo_fpga )

I got
Warning: ModelSim Altera edition is not supported by HDL Verifier
> In hdlsim>l_ParseVsimVersion at 1068
  In hdlsim>l_GetModelSimLibInfo at 527
  In hdlsim at 115
  In vsim at 106

AND:
at Modelsim:
# ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
# ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
# ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.

And:
when I simulated model at simulink :
Error reported by S-function 'shdlcosim' in 'viterbi_modelsim/viterbi_hdl/S-Function':
Failed to connect to server. Make sure the loaded HDL simulator library is using shared memory

..................................................................

I tried also
hdldaemon('socket', 0)

but the problem is still alive

would anyone like to help me regarding this problem

Thanking you
Kingsuk

Hi,

As the warning shows, the ModelSim Altera edition is not support for
cosimulation with MATLAB/Simulink. That's why you see the error message in
the ModelSim windows. For a list of supported ModelSim versions, please see
this link:

http://www.mathworks.com/help/toolbox/edalink/gs/bsm6iqf-8.html

Regards,
Tao


"Kingsuk " <kingsuk.majumdar5@gmail.com> wrote in message
news:k0hr4d$lbd$1@newscl01ah.mathworks.com...
> Sir,
> I'm using Matlab 2012a (32 bit) in my Windows 7 (64 bit) os and Altera web
> edition 9.1 (32bit)and Modelsim 6.5b (bit).
>
> When I tried to RUN MATLAB EXAMPLE: Verifying Viterbi Decoder Using
> ModelSim
> or Creating an FPGA Domain Model (dxpcSGIO301servo_fpga )
>
> I got Warning: ModelSim Altera edition is not supported by HDL Verifier
>> In hdlsim>l_ParseVsimVersion at 1068
> In hdlsim>l_GetModelSimLibInfo at 527
> In hdlsim at 115
> In vsim at 106
> AND:
> at Modelsim:
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
> ModelSim.
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
> ModelSim.
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
> ModelSim.
>
> And:
> when I simulated model at simulink : Error reported by S-function
> 'shdlcosim' in 'viterbi_modelsim/viterbi_hdl/S-Function':
> Failed to connect to server. Make sure the loaded HDL simulator library is
> using shared memory
>
> ..................................................................
>
> I tried also hdldaemon('socket', 0)
>
> but the problem is still alive
> would anyone like to help me regarding this problem
>
> Thanking you
> Kingsuk

Now I use modelsim SE 10.0c but the problem is alive .
at hdlsim.m it is written that :
% Help function to parse the returned value of executing 'vsim -version'
function [lfmBits lfmVer] = l_ParseVsimVersion(fullver)
    % parse following:
    % Model Technology ModelSim SE-64 vsim 6.1f Simulator 2006.05 May 12 2006
    % Model Technology ModelSim SE vsim 6.1f Simulator 2006.05 May 12 2006
    % QuestaSim vsim 6.2c Simulator 2006.08 Aug 26 2006
    % QuestaSim-64 vsim 6.2c Simulator 2006.08 Aug 26 2006
    % Questa Sim-64 vsim 10.0a Simulator 2011.02 Feb 17 2011
    
    % Unsupported ModelSim versions might return:
    % Model Technology ModelSim ALTERA STARTER EDITION vsim 6.5b Simulator 2009.10 Oct 1 2009
    % Model Technology ModelSim ALTERA vsim 6.5b Simulator 2009.10 Oct 1 2009
    % Model Technology ModelSim XE III vsim 6.5c Simulator 2010.02 Feb 10 2010
    if(strfind(fullver, 'ModelSim ALTERA '))
        warning(message('HDLLink:HDLSimScript:UnsupportedModelSimAE'));
    elseif(strfind(fullver,'ModelSim XE '))
        warning(message('HDLLink:HDLSimScript:UnsupportedModelSimXE'));
    end

what should I do to die out this problem ....
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
"Kingsuk" wrote in message <k0hr4d$lbd$1@newscl01ah.mathworks.com>...
> Sir,
> I'm using Matlab 2012a (32 bit) in my Windows 7 (64 bit) os and Altera web edition 9.1 (32bit)and Modelsim 6.5b (bit).
>
> When I tried to RUN MATLAB EXAMPLE: Verifying Viterbi Decoder Using ModelSim
> or
> Creating an FPGA Domain Model (dxpcSGIO301servo_fpga )
>
> I got
> Warning: ModelSim Altera edition is not supported by HDL Verifier
> > In hdlsim>l_ParseVsimVersion at 1068
> In hdlsim>l_GetModelSimLibInfo at 527
> In hdlsim at 115
> In vsim at 106
>
> AND:
> at Modelsim:
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
>
> And:
> when I simulated model at simulink :
> Error reported by S-function 'shdlcosim' in 'viterbi_modelsim/viterbi_hdl/S-Function':
> Failed to connect to server. Make sure the loaded HDL simulator library is using shared memory
>
> ..................................................................
>
> I tried also
> hdldaemon('socket', 0)
>
> but the problem is still alive
>
> would anyone like to help me regarding this problem
>
> Thanking you
> Kingsuk

I guess that your ModelSim Altera Edition shadows the ModelSim SE 10.0c .

Try this:
from windows command-line, enters "vsim" and see which version of ModelSim
is launched. If it's ModelSim Altera Edition, then you'll need to either
change the PATH environment variable so that the ModelSim SE path appears
first, or uninstall ModelSim Altera Edition.

Hope this helps.

"Kingsuk " <kingsuk.majumdar5@gmail.com> wrote in message
news:k0k6fs$6da$1@newscl01ah.mathworks.com...
> Now I use modelsim SE 10.0c but the problem is alive .
> at hdlsim.m it is written that :
> % Help function to parse the returned value of executing 'vsim -version'
> function [lfmBits lfmVer] = l_ParseVsimVersion(fullver)
> % parse following:
> % Model Technology ModelSim SE-64 vsim 6.1f Simulator 2006.05 May 12
> 2006
> % Model Technology ModelSim SE vsim 6.1f Simulator 2006.05 May 12 2006
> % QuestaSim vsim 6.2c Simulator 2006.08 Aug 26 2006
> % QuestaSim-64 vsim 6.2c Simulator 2006.08 Aug 26 2006
> % Questa Sim-64 vsim 10.0a Simulator 2011.02 Feb 17 2011
> % Unsupported ModelSim versions might return:
> % Model Technology ModelSim ALTERA STARTER EDITION vsim 6.5b Simulator
> 2009.10 Oct 1 2009
> % Model Technology ModelSim ALTERA vsim 6.5b Simulator 2009.10 Oct 1
> 2009
> % Model Technology ModelSim XE III vsim 6.5c Simulator 2010.02 Feb 10
> 2010
> if(strfind(fullver, 'ModelSim ALTERA '))
> warning(message('HDLLink:HDLSimScript:UnsupportedModelSimAE'));
> elseif(strfind(fullver,'ModelSim XE '))
> warning(message('HDLLink:HDLSimScript:UnsupportedModelSimXE'));
> end
> what should I do to die out this problem ....
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> "Kingsuk" wrote in message <k0hr4d$lbd$1@newscl01ah.mathworks.com>...
>> Sir,
>> I'm using Matlab 2012a (32 bit) in my Windows 7 (64 bit) os and Altera
>> web edition 9.1 (32bit)and Modelsim 6.5b (bit).
>>
>> When I tried to RUN MATLAB EXAMPLE: Verifying Viterbi Decoder Using
>> ModelSim
>> or Creating an FPGA Domain Model (dxpcSGIO301servo_fpga )
>>
>> I got Warning: ModelSim Altera edition is not supported by HDL Verifier
>> > In hdlsim>l_ParseVsimVersion at 1068
>> In hdlsim>l_GetModelSimLibInfo at 527
>> In hdlsim at 115
>> In vsim at 106 AND:
>> at Modelsim:
>> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
>> ModelSim.
>> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
>> ModelSim.
>> # ** Error: (vsim-FLI-3155) The FLI is not enabled in this version of
>> ModelSim.
>>
>> And:
>> when I simulated model at simulink : Error reported by S-function
>> 'shdlcosim' in 'viterbi_modelsim/viterbi_hdl/S-Function':
>> Failed to connect to server. Make sure the loaded HDL simulator library
>> is using shared memory
>>
>> ..................................................................
>>
>> I tried also hdldaemon('socket', 0)
>>
>> but the problem is still alive would anyone like to help me regarding
>> this problem
>>
>> Thanking you
>> Kingsuk
>

Thank you for your kind help to die out this problem ...

With regards
Kingsuk

Thank You for your kind help to die out this problem...

With regards

Kingsuk

Sir,

I have Matlab2012a and "Altera cyclone" (EP1C12Q240C8) FPGA kit.

 I have to use Altera Quartus II version 9.1 (and tried with 10.0 also) and Altera DSP Builder 9.1 (and tried with 10.0 also).
But when I installed DSP builder and tried to open Matlab -->simulink-->Altera DSP block
Then Matlab uncounted some problems and is needed to be closed.

e.g.
In C:\MATLAB\R2012a\toolbox\simulink\simulink\private\lb_createSubSystemIcons.p>lb_createSubSystemIcons at 12
  In slprivate at 12
Warning: Could not evaluate MaskDisplay commands of block 'Control/latch_0L/SampleDelay':
Subscript indices must either be real positive integers or logicals.

(Like this)



I can't find out Altera Quartus II version 11.0 from there site. There are Altera Quartus II version 11.0sp1 and 11.0sp2.
And in version 12.0 "cyclone family" is not available

Would anyone like to suggest me to die out this problem?

With Regards
Kingsuk Majumdar


 

Sir
I have:
OS: Windows 7 (64bit)
Matlab : 2012a(32bit)
Altera Quartus II (web edition) : 11.0sp1 (32bit)
ModelSim SE : 10.0c(32bit)
FPGA kit: Altera Cyclone (EP1C12Q240C8) (Cyclone Family)
Altera DSP builder: 11.0sp1 (32bit)
C compiler: lcc

1. Problem during Altera DSP builder installation :
In Matlab command window:
There are many "Altelink2" files [like this as warning]
asked to check : "which –all Altelink2"
2. Problem during running Simulink:
A. open Matlab-->simulin--> Libraries:
There are two Altera blocks:
a) "Altera DSP Builder Advanced Blockset " (with sub directories as it has "+" sign in the leftside)
b) "Altera DSP Builder Blockset" (without any sub directories as it has no any "+" sign in the left side)
B. When I click on "Altera DSP Builder Blockset" . There is no block set.
C. After some time Matalb noticed me: MATLAB uncounted some unexpected problems and needs to be closed no now. There is "matlab_crash_dump.3132.0" file at your temp directory. (like that)
{I'm facing same problem with Altera Quartus II & Altera DSP Builder version 9.1, 10.0 also and Altera Quartus II version 12.0 or higher version does not have "Cyclone family" and Altera Quartus II 11.0 (which is recommended by Matlab 2012a is not available on their site (www.altera.com) )}
What should I do to fix these problems?
I have to do my project with this FPGA kit and Matlab
I am looking forward to receive your kind replay regarding this subject


With Regards
Kingsuk Majumdar

Sir,
I'm facing another problem regarding "HDL workflow Advisor" :
perform Logic Synthesis:
status : Failed

info:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Failed Logic Synthesis.
Synthesis Tool Log:
Downstream Integration: Run Synthesis Attempt Unsuccessful
Synthesis Tool Log:
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2011 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Altera Program License
    Info: Subscription Agreement, Altera MegaCore Function License
    Info: Agreement, or other applicable license agreement, including,
    Info: without limitation, that your use is for the sole purpose of
    Info: programming logic devices manufactured by Altera and sold by
    Info: Altera or its authorized distributors. Please refer to the
    Info: applicable agreement for further details.
    Info: Processing started: Wed Sep 19 16:52:44 2012
Info: Command: quartus_sta -t Subsystem_Altera_QUARTUS_II_run.tcl
### Open existing Altera QUARTUS II 11.0 project hdlUltitle_prj\quartus_prj\Subsystem_quartus.qpf
### Running Synthesis in Altera QUARTUS II 11.0 ...
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 19 16:52:48 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Subsystem_quartus -c Subsystem_quartus
Warning: Parallel compilation is not licensed and has been disabled
Info: Found 2 design units, including 1 entities, in source file /fpga/fpgamatlab2011b/usingmatlabwf/pwmtest/hdlultitle_prj/hdlsrc/subsystem.vhd
    Info: Found design unit 1: Subsystem-rtl
    Info: Found entity 1: Subsystem
Info: Elaborating entity "Subsystem" for the top level hierarchy
Error (10414): VHDL Unsupported Feature error at Subsystem.vhd(30): cannot synthesize non-constant real objects or values File: E:/FPGA/FPGAMATLAB2011b/USINGMATLABWF/PWMTEST/hdlUltitle_prj/hdlsrc/Subsystem.vhd Line: 30
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
    Error: Peak virtual memory: 283 megabytes
    Error: Processing ended: Wed Sep 19 16:52:52 2012
    Error: Elapsed time: 00:00:04
    Error: Total CPU time (on all processors): 00:00:04
------------------------------------------------
ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.

    while executing
"execute_module -tool map"
    (file "Subsystem_Altera_QUARTUS_II_run.tcl" line 21)
------------------------------------------------
Error: Evaluation of Tcl script Subsystem_Altera_QUARTUS_II_run.tcl unsuccessful
Error: Quartus II TimeQuest Timing Analyzer was unsuccessful. 8 errors, 1 warning
    Error: Peak virtual memory: 210 megabytes
    Error: Processing ended: Wed Sep 19 16:52:53 2012
    Error: Elapsed time: 00:00:09
    Error: Total CPU time (on all processors): 00:00:03

Elapsed time is 9.2233 seconds.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

would anyone like to help me regarding this case ..


With Regards
Kingsuk

You might have double data type, which is not supported in synthsis, in your
generated HDL code. It would be more helpful if you can attached this file:
E:/FPGA/FPGAMATLAB2011b/USINGMATLABWF/PWMTEST/hdlUltitle_prj/hdlsrc/Subsystem.vhd


"Kingsuk " <kingsuk.majumdar5@gmail.com> wrote in message
news:k3calc$dql$1@newscl01ah.mathworks.com...
> Sir,
> I'm facing another problem regarding "HDL workflow Advisor" :
> perform Logic Synthesis:
> status : Failed
>
> info:
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Failed Logic Synthesis.
> Synthesis Tool Log: Downstream Integration: Run Synthesis Attempt
> Unsuccessful
> Synthesis Tool Log:
> Info: *******************************************************************
> Info: Running Quartus II TimeQuest Timing Analyzer
> Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
> Info: Copyright (C) 1991-2011 Altera Corporation. All rights reserved.
> Info: Your use of Altera Corporation's design tools, logic functions
> Info: and other software and tools, and its AMPP partner logic Info:
> functions, and any output files from any of the foregoing Info: (including
> device programming or simulation files), and any Info: associated
> documentation or information are expressly subject Info: to the terms and
> conditions of the Altera Program License Info: Subscription Agreement,
> Altera MegaCore Function License Info: Agreement, or other applicable
> license agreement, including, Info: without limitation, that your use is
> for the sole purpose of Info: programming logic devices manufactured by
> Altera and sold by Info: Altera or its authorized distributors. Please
> refer to the Info: applicable agreement for further details.
> Info: Processing started: Wed Sep 19 16:52:44 2012
> Info: Command: quartus_sta -t Subsystem_Altera_QUARTUS_II_run.tcl
> ### Open existing Altera QUARTUS II 11.0 project
> hdlUltitle_prj\quartus_prj\Subsystem_quartus.qpf
> ### Running Synthesis in Altera QUARTUS II 11.0 ...
> Info: *******************************************************************
> Info: Running Quartus II Analysis & Synthesis
> Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
> Info: Processing started: Wed Sep 19 16:52:48 2012
> Info: Command:
> quartus_map --read_settings_files=on --write_settings_files=off
> Subsystem_quartus -c Subsystem_quartus
> Warning: Parallel compilation is not licensed and has been disabled
> Info: Found 2 design units, including 1 entities, in source file
> /fpga/fpgamatlab2011b/usingmatlabwf/pwmtest/hdlultitle_prj/hdlsrc/subsystem.vhd
> Info: Found design unit 1: Subsystem-rtl
> Info: Found entity 1: Subsystem
> Info: Elaborating entity "Subsystem" for the top level hierarchy
> Error (10414): VHDL Unsupported Feature error at Subsystem.vhd(30): cannot
> synthesize non-constant real objects or values File:
> E:/FPGA/FPGAMATLAB2011b/USINGMATLABWF/PWMTEST/hdlUltitle_prj/hdlsrc/Subsystem.vhd
> Line: 30
> Error: Can't elaborate top-level user hierarchy
> Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1
> warning
> Error: Peak virtual memory: 283 megabytes
> Error: Processing ended: Wed Sep 19 16:52:52 2012
> Error: Elapsed time: 00:00:04
> Error: Total CPU time (on all processors): 00:00:04
> ------------------------------------------------
> ERROR: Error(s) found while running an executable. See report file(s) for
> error message(s). Message log indicates which executable was run last.
>
> while executing
> "execute_module -tool map"
> (file "Subsystem_Altera_QUARTUS_II_run.tcl" line 21)
> ------------------------------------------------
> Error: Evaluation of Tcl script Subsystem_Altera_QUARTUS_II_run.tcl
> unsuccessful
> Error: Quartus II TimeQuest Timing Analyzer was unsuccessful. 8 errors, 1
> warning
> Error: Peak virtual memory: 210 megabytes
> Error: Processing ended: Wed Sep 19 16:52:53 2012
> Error: Elapsed time: 00:00:09
> Error: Total CPU time (on all processors): 00:00:03
>
> Elapsed time is 9.2233 seconds.
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> would anyone like to help me regarding this case ..
>
>
> With Regards Kingsuk
>

Sir,

yes that is double data type.
I have attached that file herewith

-- -------------------------------------------------------------
--
-- File Name: hdlUltitle_prj\hdlsrc\Subsystem.vhd
-- Created: 2012-09-19 16:49:40
--
-- Generated by MATLAB 7.13 and Simulink HDL Coder 2.2
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 5e-008
-- Target subsystem base rate: 5e-008
--
-- -------------------------------------------------------------


-- -------------------------------------------------------------
--
-- Module: Subsystem
-- Source Path: untitled/Subsystem
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY Subsystem IS
  PORT( Out1 : OUT real -- double
        );
END Subsystem;


ARCHITECTURE rtl OF Subsystem IS

  -- Signals
  SIGNAL Constant1_out1 : real := 0.0; -- double
  SIGNAL Constant_out1 : real := 0.0; -- double
  SIGNAL Sum_out1 : real := 0.0; -- double

BEGIN
  Constant1_out1 <= 2.0;

  Constant_out1 <= 1.0;

  Sum_out1 <= Constant1_out1 + Constant_out1;

  Out1 <= Sum_out1;

END rtl;

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

My system
MATLAB : 2011b (32 bit)
OS: Windows 7 (64bit)
Altera Quartus II : 11.0sp1 (web Edition)
Modelsim: 10.0c SE
FPGA kit : Altera Cyclone family (EP1C12Q240C8)

would you like to help me to die out this problem.

With Regards

Kingsuk

Sir,

I convert manually all values in fix-point in "Signal Attributes" in block parameters then this problem is solved. But I want some tool or command that convert all values in fix-point.


With regards

Kingsuk