| Files Posted by Igal |
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| 17 Dec 2012 |
|
Bit Packet Analyzer The Bit Packet Analyzer can be used to analyze bit streams for repeating patterns (e.g. preamble)
Author: Igal |
communications, signal processing, gui, bit, packet |
9 |
0 |
|
| 26 Feb 2012 |
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Simulink model for Fetal ECG extraction (HDL Compatible algorithm) This is an HDL Coder compatible Fetal ECG extraction algorithm.
Author: Igal |
biotech, demo, signal processing, simulation, simulink, medical |
50 |
0 |
4.0 |
1 rating
|
| 06 Sep 2011 |
|
HDL Coder Compatible edge detector Simulink HDL Coder compatible negative and positive edge detectors.
Author: Igal |
hdl, edge, verilog, vhdl, simulink |
6 |
0 |
|
| 05 Sep 2011 |
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HDL coder compatible 1D Positive and Negative edge detectors The default 1D Simulink edge detector is not HDl Coder compatible, so here's an alternative.
Author: Igal |
edge, logic, hdl coder, verilog, vhdl |
2 |
0 |
|
| 26 Apr 2011 |
|
IEEE single precision floating point number <=> uint 32 converter C based S-Function blocks implementing biderectional convertion single precision floats <=> uint32
Author: Igal |
fpga, floating point core, ieee single, uint32, control design, signal processing |
3 |
0 |
|
| Files Tagged by Igal |
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| 17 Dec 2012 |
|
Bit Packet Analyzer The Bit Packet Analyzer can be used to analyze bit streams for repeating patterns (e.g. preamble)
Author: Igal |
communications, signal processing, gui, bit, packet |
9 |
0 |
|
| 26 Feb 2012 |
|
Simulink model for Fetal ECG extraction (HDL Compatible algorithm) This is an HDL Coder compatible Fetal ECG extraction algorithm.
Author: Igal |
biotech, demo, signal processing, simulation, simulink, medical |
50 |
0 |
4.0 |
1 rating
|
| 06 Sep 2011 |
|
HDL Coder Compatible edge detector Simulink HDL Coder compatible negative and positive edge detectors.
Author: Igal |
hdl, edge, verilog, vhdl, simulink |
6 |
0 |
|
| 05 Sep 2011 |
|
HDL coder compatible 1D Positive and Negative edge detectors The default 1D Simulink edge detector is not HDl Coder compatible, so here's an alternative.
Author: Igal |
edge, logic, hdl coder, verilog, vhdl |
2 |
0 |
|
| 26 Apr 2011 |
|
IEEE single precision floating point number <=> uint 32 converter C based S-Function blocks implementing biderectional convertion single precision floats <=> uint32
Author: Igal |
fpga, floating point core, ieee single, uint32, control design, signal processing |
3 |
0 |
|
| Files Matching Igal's Watch List |
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| Updated |
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File |
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Downloads (last 30 days) |
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| 17 Dec 2012 |
|
Bit Packet Analyzer The Bit Packet Analyzer can be used to analyze bit streams for repeating patterns (e.g. preamble)
Author: Igal |
communications, signal processing, gui, bit, packet |
9 |
0 |
|
| 06 Sep 2011 |
|
HDL Coder Compatible edge detector Simulink HDL Coder compatible negative and positive edge detectors.
Author: Igal |
hdl, edge, verilog, vhdl, simulink |
6 |
0 |
|
| 26 Apr 2011 |
|
IEEE single precision floating point number <=> uint 32 converter C based S-Function blocks implementing biderectional convertion single precision floats <=> uint32
Author: Igal |
fpga, floating point core, ieee single, uint32, control design, signal processing |
3 |
0 |
|
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