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Arun


Tenesix Inc.

Last seen: 2 years ago |  Active since 2014

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Question


HDL Coder RAM generation for an array
will hdl coder generate ram for 2 dimension array if isempty(my_ary) my_ary = zeros (10,1000) end new_value = [1:10...

9 years ago | 1 answer | 0

1

answer

Question


Matlab to RTL - Block RAM Enable
An array will get recognized as block RAM. So foo_ary(index) = write_value_at_index will write to the block RAM Question - how...

9 years ago | 2 answers | 0

2

answers

Question


No of Pipeline Stages in Verilog coming from an m file (or latency)
How does one find how many pipeline stages exist in the verilog file. Example, run the mdhlc_sobel filter example from the web s...

9 years ago | 2 answers | 0

2

answers

Question


HDL Resource Untilization does not match Synthsis Ouput
When running hdl coder for example on mlhdlc_sobelfilter.m the utilization report says the hdl needs multipliers (90) adders/Sub...

9 years ago | 1 answer | 0

1

answer