Statistics
3 Questions
0 Answers
RANK
95,987
of 289,751
REPUTATION
0
CONTRIBUTIONS
3 Questions
0 Answers
ANSWER ACCEPTANCE
66.67%
VOTES RECEIVED
0
RANK
of 19,582
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 144,135
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Accept 1 answer given by other contributors
Awarded to smiczh ZHOU on 20 Jul 2017
Feeds
Question
Buffer and enable in simulink
Put buffer block and enable in a subsystem. Suppose step = 1, buffersize = 9 and enable signal is effective in 1.5s ~ 9.5s. So I...
13 years ago | 0 answers | 0
0
answersQuestion
How to build a simulink model which can generate HDL coder to resize images or videos?
I want to resize images or videos by FPGA. I only know the resize block but it cannot generate HDL code. Anybody can teach me or...
13 years ago | 4 answers | 0
4
answersQuestion
The demo of hdlcoder_sobel_serial_eml.mdl
In the sobel_edge_eml of sobel_edge_hardware of hdlcoder_sobel_serial_eml.mdl, there are three inputs u, thresh and C in the fun...
13 years ago | 1 answer | 0
1
answer
You can also select a web site from the following list
Americas
- América Latina (Español)
- Canada (English)
- United States (English)
Europe
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)
Asia Pacific
- Australia (English)
- India (English)
- New Zealand (English)
- 中国
- 日本Japanese (日本語)
- 한국Korean (한국어)