How can I set properties such as Verilog Include Directories in the FILWIZARD of HDL Verifier 4.1 (R2012b)?

I am using the FILWIZARD to generate and simulate a Xilinx FPGA block, according to my hardware description source files that are written in, e.g., Verilog. Non-MathWorks products, e.g., the Xilinx TCL scripting interface, are equipped with the functionality of setting multiple options, such as the Verilog Include Directories. How can I do that in FILWIZARD?

Answer 1

[MathWorks Support Team]

The FILWIZARD in HDL Verifier 4.1 (R2012b) can accept TCL scripts together with HDL or Verilog files in its "Source Files" pane. Such TCL scripts can contain commands that can also be executed by software such as the Xilinx TCL scripting interface.

For example, to specify the Verilog Include Directories in FILWIZARD, include a TCL script in its Source Files pane, that includes the following command:

       project set "Verilog Include Directories" "..//include" -process "Synthesize - XST"

The pathname "..//include" is the relative path to the include directory.

For releases prior to R2012b, the option to include custom TCL Code into the FIL Wizard is not available in the EDA Simulator Link. There are no workarounds.