Why can I not I set the port I/O mode of my VHDL Cosimulation block to be "INOUT" in Link for ModelSim?

I would like to change the port I/O Mode of my VHDL Cosimulation block to be "INOUT" in Link for ModelSim. ModelSim allows me to set their direction to be "INOUT" in the VHDL code.

Answer 1

[MathWorks Support Team]

This enhancement has been incorporated in Release 2006b (R2006b). For previous product releases, read below for any possible workarounds:

The ability to define the port's I/O Mode to be "INOUT" is not available in Link for ModelSim.

To work around this issue, specify the same signal as both a Simulink input and Simulink output in the Cosimulation block.