simplify Xilinx Block input ports in Simulink

Hello.

I have a (own written and synthesized ) Xilinx Block (XSG Block) in Simulink with an array as input. For each possible Value in the array you get one input port on the XSG Block. An Array with a dimension of 10 entails that 10 inputs ports appear on the XSG Block for instance. So the number of input ports depends on the size of the array.

Now i wanna structure my project for a dynamic array dimension. Is there a possibility to combine the input ports on the XSG Block to one input?

Maybe that i have a Buffer with a dynamic size whom i connect with the dynamic input port of my XSG Block (through a Bus or something else)?

Hope you could follow me and thank you in advance!

Greeds Philip