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HDL Coder with Xilinx Sysgen R2013b

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Richard
Richard on 3 May 2014
Closed: MATLAB Answer Bot on 20 Aug 2021
Hello,
I have a design which uses both Simulink blocks and Xilinx System Generator blocks. As I understand it, to get this design converted to HDL, I need to use black boxes to convert the Simulink blocks into SysGen blocks. I can then use the SysGen token to generate the HDL.
The process I take is to first create HDL out of the Simulink blocks. I then add a Xilinx SysGen black box and connect the top level HDL files created in the previous step. When I try to connect this block to the rest of the design, the output wires will not form a connection with any existing wires in the design. I also don't know what to connect the CLK and Enable lines to that exist on the new black box unit.
The big question I'm posing is, how do I get a hybrid design, as I've described above through HDL coder?
Your help is appreciated, Rich
  1 Comment
Yongfeng
Yongfeng on 5 May 2014
XilinxSystemGeneratorSubsystem is the recommended way to integrate SysGen blocks in HDL Coder. Please refer to this paper for details: http://www.mathworks.com/tagteam/74244_92077v00_Xilinx_WhitePaper_final.pdf.

Answers (1)

Kiran Kintali
Kiran Kintali on 24 May 2021
Using Xilinx® System Generator for DSP with HDL Coder™
This example shows how to use Xilinx System Generator for DSP with HDL Coder.
Using the Xilinx System Generator Subsystem block enables you to model designs using blocks from both Simulink® and Xilinx, and to automatically generate integrated HDL code. HDL Coder™ generates HDL code from the Simulink blocks, and uses Xilinx System Generator to generate HDL code from the Xilinx System Generator Subsystem blocks.
In this example, the design, or code generation subsystem, contains two parts: one with Simulink native blocks, and one with Xilinx blocks. The Xilinx blocks are grouped into a Xilinx System Generator Subsystem sysgendut that is inside a SLandSysGen Subsystem at the top level of the model hdlcoder_slsysgen. System Generator optimizes these blocks for Xilinx FPGAs. In the rest of the design, Simulink blocks and HDL Coder offer model-based design capabilities and HDL optimizations, such as distributed pipelining and delay balancing

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