how to use an external memory(ddr2, dpram) in HDL coder by matlab??

I am trying to convert an image process matlab code to vhdl code. I use a hdl coder by matlab code. but, I cann't find how to access the external memory(such as DDR2, DPRAM) in hdl coder.

Please help me~~~~

Answer 1

[Kiran Kintali]

Performing Large Matrix Operation on FPGA using External Memory

web(fullfile(docroot, 'hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-external-memory.html'))

https://www.mathworks.com/help/hdlcoder/examples/performing-large-matrix-operation-on-fpga-using-external-memory.html

This HDL Coder example shows how to generate an HDL IP core with AXI4 Master interface, perform matrix multiplication in HDL IP core, and write output result to DDR memory.

[Brian]

Hi Kiran,

When I clicked on your html example link, I got the message "The page you were looking for does not exist. Use the search box or browse topics below to find the page you were looking for."

However, I am not looking to do matrix operations, just displaying an image over HDMI. What I need help with is for MathWorks to provide a generic HDL DDR memory controller using HDL Coder, but without a processor. All HDL, using StateFlow or Simulink.

Does MathWorks have that kind of reference design?

[Tom Mealey]

Hi Brian,

We do not have any examples of a memory controller that interfaces directly with the physical DDR pins. The example that Kiran linked implements an AXI4 Master which connects to the AXI4 Slave interface of a memory controller. Here is a corrected version of that link:

https://www.mathworks.com/help/hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-external-memory.html

Specifically, this example uses a Vivado reference design for ZC706 and ZCU102 boards which contains the Xilinx Memory Interface Generator (MIG) IP core to implement the DDR controller. You should be able to use this IP core, or similar one in your EDA tool, to implement a DDR controller with AXI4 Slave interface. Then implement your logic to read/write memory addresses using the simplified AXI4 protocol in Simulink:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-master-interface-generation.html

Hope this helps,

Tom